Delta-Sigma (ΔΣ) ADCs generate a continuous stream of output values irrespective of the actual needs of a control algorithm. Because of the continuous generation of output, it is not uncommon that many samples are discarded as unnecessary. However, regardless of whether the sample is used or not, each sample generates an interrupt to a central processing unit (CPU) or Microprocessor unit (MPU), which results in wasted cycles servicing an interrupt service request (ISR) that provides no benefit. When a Delta-Sigma ADC is used for motor control, typically three to ten interrupts occur per pulse width modulation (PWM) cycle, many or most of which are not necessary.
Previously, a small amount of code has been used at the processing unit to keep track of unwanted samples and free the processing unit as quickly as possible. Alternatively, a small first-in first-out (FIFO) buffer has been used to collect a given number of samples before generating an interrupt, which allows fewer interrupts but does not deal with the problem of sending data that will only be discarded. It would be desirable to provide a method of interrupting the CPU/MPU only when useful work can be accomplished.